Reservoir Computing with Nonlinear Micro-Resonators on a Silicon Photonics Chip
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We present here recent advances in the use of a small network of nonlinear micro-resonators integrated on a Silicon chip as a reservoir computer. We provide numerical evidence that this novel photonic integrated circuit can perform binary-type tasks (e.g.: the XOR task or multi-bit header recognition task) at bitrate of 20 Gb/s with a performance level adequate for telecom applications. We analyze the impact of key operational parameters (e.g.: optical power injected) and topological properties of the network on the level of performance of the proposed architecture. Finally, we will compare the performance between this new chip with a previous generation of passive reservoir  realized with splitters and combiners without any internal nonlinearity.