Reservoir Computing with Nonlinear Micro-Resonators on a Silicon Photonics Chip

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dc.contributor.authorRontani, Damien
dc.contributor.authorKatumba, Andrew
dc.contributor.authorFreiberger, Matthias
dc.contributor.authorDambre, Joni
dc.contributor.authorBienstman, Peter
dc.contributor.authorSciamanna, Marc
dc.date.accessioned2022-12-01T18:32:01Z
dc.date.available2022-12-01T18:32:01Z
dc.date.issued2017
dc.description.abstractWe present here recent advances in the use of a small network of nonlinear micro-resonators integrated on a Silicon chip as a reservoir computer. We provide numerical evidence that this novel photonic integrated circuit can perform binary-type tasks (e.g.: the XOR task or multi-bit header recognition task) at bitrate of 20 Gb/s with a performance level adequate for telecom applications. We analyze the impact of key operational parameters (e.g.: optical power injected) and topological properties of the network on the level of performance of the proposed architecture. Finally, we will compare the performance between this new chip with a previous generation of passive reservoir [1] realized with splitters and combiners without any internal nonlinearity.en_US
dc.identifier.citationRontani, D., Coarer, D. L., Katumba, A., Freiberger, M., Dambre, J., Bienstman, P., & Sciamanna, M. (2017). Reservoir computing with nonlinear micro-resonators on a silicon photonics chip. In NOLTA 2017 (pp. 253-255).en_US
dc.identifier.urihttps://biblio.ugent.be/publication/8664732/file/8664734
dc.identifier.urihttps://nru.uncst.go.ug/handle/123456789/5631
dc.language.isoenen_US
dc.publisherNOLTAen_US
dc.titleReservoir Computing with Nonlinear Micro-Resonators on a Silicon Photonics Chipen_US
dc.typeOtheren_US
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